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FIN324CGFX Datenblatt(PDF) 7 Page - Fairchild Semiconductor

Teilenummer FIN324CGFX
Bauteilbeschribung  24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN324CGFX Datenblatt(HTML) 7 Page - Fairchild Semiconductor

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© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN324C Rev. 1.0.5
7
LV-CMOS I/O Signals
System Control Signals
The system control signals consist of M/S, /RES,
/STBY(SLEW), PAR/SPI, and CKSEL. For connectivity
flexibility, these signals are over-voltage tolerant to the
maximum supply voltage connected to the device. This
allows these signals to be tied HIGH to either a VDDS or
VDDP supply without static current consumption. These
signals are all LV-CMOS inputs and should never be
allowed to float.
Parallel I/O Signals
The parallel data port signals consist of the DP[17:0],
CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals.
These signals have built-in voltage translation, allowing
the signals of the master and slave to be connected to
different VDDP supply voltages.
Serial I/O Signals
CTL I/O Technology
The serial I/O is implemented using Fairchild’s
proprietary differential CTL I/O technology. During data
transfers, the serial I/O are powered up to a normal
operating mode around .5V. Upon completion of a data
transfer, the serial I/O goes to a lower power mode
around VDDS.
Serial I/O Orientation Logic
The serial I/O signal traces should not cross between
the master and the slave. The pin locations have been
designed to eliminate the need to cross traces. See
Table 7, Figure 4 and Figure 5.
Table 7. Serial Pin Orientation
Master (M/S=1) (Pad/Pin #)
Slave (M/S=0) (Pad/Pin #)
Package
CKS+
CKS-
DS-
DS+
CKS+
CKS-
DS-
DS+
MLP
2
3
6
7
7
6
3
2
BGA
D1
E1
F1
G1
G1
F1
E1
D1
BGA
Slave
A
B
C
D
E
F
G
1
2
3
456
<DS+>
<DS->
<CKS->
<CKS+>
BGA
Master
G
F
E
D
C
B
A
DS-
CKS-
CKS+
6
5
4
321
DS+
21
22
23
24
25
26
27
28
29
30
10
9
8
7
6
5
4
3
2
1
2
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
MLP
Master
M/S
PAR/SPI
/RES
DS+
DS-
VDDA
VDDS
CKS-
CKS+
CKSEL(H)
MLP
Slave
CKSEL(H)
(DS+)
(DS-)
VDDS
VDDA
(CKS-)
(CKS+)
/RES
PAR/SPI
M/S
Figure 4.
BGA Pair
Figure 5.
MLP Pair


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