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MC10E197 Datenblatt(PDF) 2 Page - ON Semiconductor

Teilenummer MC10E197
Bauteilbeschribung  5V ECL Data Separator
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10E197 Datenblatt(HTML) 2 Page - ON Semiconductor

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MC10E197
http://onsemi.com
2
Pinout: 28-Lead PLCC
(Top View)
25 24
23
22
21
20
19
18
17
16
15
14
13
12
56
7
8
9
10
11
26
27
28
2
3
4
RDCLK
RDCLK
VCC
RSDATA
RSDATA
PUMPUP
RSETDN
TEST
EXTVCO
ENVCO
VEE
ACQ
TYPE
RDEN
1
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
* All VCC and VCCOX pins are tied together on the die.
PIN DESCRIPTIONS
PIN
FUNCTION
REFCLK
ECL Reference clock equivalent to one clock cycle per decoding window.
REFCLK
ECL Reference clock equivalent to one clock cycle per decoding window.
RDEN
ECL Enable data synchronizer when HIGH. When LOW enable the phase/frequency detector steered by REFCLK.
RAWD
ECL Data Input to Synchronizer logic.
VCOIN
ECL VCO control voltage input
CAP1/CAP2
ECL VCO frequency controlling capacitor inputs
ENVCO
ECL VCO select pin. LOW selects the internal VCO and HIGH selects the external VCO input. Pin floats LOW when left open.
EXTVCO
ECL External VCO pin selected when ENVCO is HIGH
ACQ
ECL Acquisition circuitry select pin. This pin must be driven HIGH at the end of the data sync field for some sync field types.
TYPE
ECL Selects between the two types of commonly used sync fields. When LOW it selects a sync field interspersed with 3
zeroes (2:7 RLL code). When HIGH it selects a sync field interspersed with 2 zeroes (1:7 RLL code).
TEST
ECL Input included to initialize the clock flip-flop for test purposes only. Pin should be left open (LOW) in actual application.
PUMPUP
ECL Open collector charge pump output for the signal pump
PUMPDN
ECL Open collector charge pump output for the reference pump
RSETUP
ECL Current setting resistor for the signal pump
RSETDN
ECL Current setting resistor for the reference pump
RDATA
ECL Synchronized data output
RDCLK
ECL Synchronized clock output
VCC, VCCOX,
VCCVCO
Most positive supply rails. Digital and analog supplies are independent on chip
VEE, VEEVCO
Most negative supply rails. Digital and analog supplies are independent on chip
INTERNAL
VCO
DATA
PHASE
DETECTOR
ACQUISITION
CIRCUITRY
CHARGE
PUMP
CURRENT-
SOURCES
PHASE
DETECTOR
MUX
PHASE FREQUEN-
CY DETECTOR
LOGIC DIAGRAM
RDEN
REFCLK
VCOIN
EXTVCO
ENVCO
RAWD
ACQ
TYPE
CAP1
CAP2
PUMPUP
PUMPDN
RSETUP
RSETDN
RDATA
RDCLK
VCO
MUX
CLOCK &
DATA
BUFFER


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