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MC10EP35DG Datenblatt(PDF) 1 Page - ON Semiconductor |
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MC10EP35DG Datenblatt(HTML) 1 Page - ON Semiconductor |
1 / 11 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 5 1 Publication Order Number: MC10EP35/D MC10EP35, MC100EP35 3.3V / 5VECL JK Flip−Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation. Features • 410 ps Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V • Open Input Default State • Q Output Will Default LOW with Inputs Open or at VEE • Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. H = MC10 A = Assembly Location K = MC100 L = Wafer Lot 5R = MC10 Y = Year 3M = MC100 W = Work Week M = Date Code G = Pb−Free Package ALYWG G HP35 ALYWG G KP35 MARKING DIAGRAMS* SOIC−8 D SUFFIX CASE 751 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 1 8 See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION http://onsemi.com 1 8 HEP35 ALYW G 1 8 KEP35 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 14 (Note: Microdot may be in either location) |
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