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MC10H161 Datenblatt(PDF) 1 Page - ON Semiconductor |
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MC10H161 Datenblatt(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 7 1 Publication Order Number: MC10H161/D MC10H161 Binary to 1−8 Decoder (Low) Description The MC10H161 provides parallel decoding of a three bit binary word to one of eight lines. The MC10H161 is useful in high−speed multiplexer/demultiplexer applications. The MC10H161 is designed to decode a three bit input word to one of eight output lines. The MC10H161 output will be low when selected while all other output are high. The enable inputs, when either or both are high, force all outputs high. The MC10H161 is a true parallel decoder. This eliminates unequal parallel path delay times found in other decoder designs. These devices are ideally suited for multiplexer/demultiplexer applications. Features • Propagation Delay, 1.0 ns Typical • Power Dissipation, 315 mW Typical (same as MECL 10K™) • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K Compatible • Pb−Free Packages are Available* LOGIC DIAGRAM DIP PIN ASSIGNMENT VCC1 E0 Q3 Q2 Q1 Q0 A VEE VCC2 E1 C Q4 Q5 Q6 Q7 B 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC1 = Pin 1 VCC2 = Pin 16 VEE = Pin 8 E02 E115 A7 B9 C14 6Q0 5Q1 4Q2 3Q3 13Q4 12Q5 11Q6 10Q7 H H H H L H H H H H L L L L L L L L X H TRUTH TABLE ENABLE INPUTS INPUTS OUTPUTS L L L L L L L L H X L L L L H H H H X X L L H H L L H H X X L H L H L H L H X X L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H Q4 E0 E1 C B A Q0 Q1 Q2 Q3 Q5 Q6 Q7 Pin assignment is for Dual−in−Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. CDIP−16 L SUFFIX CASE 620A MARKING DIAGRAMS* PDIP−16 P SUFFIX CASE 648 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION SOEIAJ−16 CASE 966 16 1 16 1 MC10H161P AWLYYWWG 1 16 MC10H161L AWLYYWW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G= Pb−Free Package 10H161 ALYWG PLLC−20 FN SUFFIX CASE 775 20 1 10H161G AWLYYWW 120 |
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