MC100EP016A

http://onsemi.com

3

Figure 2. 8-BIT Binary Counter Logic Diagram

Note that this diagram is provided for understanding of logic operation only.

It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.

SLAVE

MASTER

5

TC

P7

CE Q

0

BIT 1

CE

Q0M

Q0M

PE

TCLD

CE

MR

CLK

BIT 7

BITS 2−6

CLK

COUT

COUT

BIT 0

Table 4. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 kW

Internal Input Pullup Resistor

N/A

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Pb Pkg

Pb−Free Pkg

LQFP−32

Level 2

Level 2

Flammability Rating Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

1226 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.