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MC100EP40DTR2G Datenblatt(PDF) 1 Page - ON Semiconductor

Teilenummer MC100EP40DTR2G
Bauteilbeschribung  3.3V / 5V ECL Differential Phase?묯requency Detector
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Hersteller  ONSEMI [ON Semiconductor]
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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 10
1
Publication Order Number:
MC100EP40/D
MC100EP40
3.3V / 5VECL Differential
Phase−Frequency Detector
Description
The MC100EP40 is a three−state phase−frequency detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V / 5 V power supply.
When Reference (R) and Feedback (FB) inputs are unequal in
frequency and/or phase the differential UP (U) and DOWN (D)
outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO.
When Reference (R) and Feedback (FB) inputs are 80 ps or less in
phase difference, the Phase Lock Detect pin will indicate lock by a
high state (VOH). The VTX (VTR, VTR, VTFB, VTFB) pins offer an
internal termination network for 50
W line impedance environment
shown in Figure 2. An external sinking supply of VCC−2 V is required
on VTX pin(s). If you short the two differential VTR and VTR (or VTFB
and VTFB) together, you provide a 100 W termination resistance that is
compatible with LVDS signal receiver termination. For more
information on termination of logic devices, see AND8020.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
For more information on Phase Lock Loop operation, refer to
AND8040.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
Features
Maximum Frequency > 2 GHz Typical
Fully Differential
Advanced High Band Output Swing of 400 mV
Theoretical Gain = 1.11
Trise 97 ps Typical, Ffall 70 ps Typical
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
50 W Internal Termination Resistor
These are Pb−Free Devices
MARKING
DIAGRAM*
TSSOP−20
DT SUFFIX
CASE 948E
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
20
1
http://onsemi.com
(Note: Microdot may be in either location)
100
EP40
ALYW G
1
20
G
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
*For additional marking information, refer to
Application Note AND8002/D.


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