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MC10124P Datenblatt(PDF) 1 Page - ON Semiconductor

Teilenummer MC10124P
Bauteilbeschribung  Quad TTL to MECL Translator
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10124/D
MC10124
Quad TTL to MECL
Translator
The MC10124 is a quad translator for interfacing data and control
signals between a saturated logic section and the MECL section of
digital systems. The MC10124 has TTL compatible inputs, and
MECL complementary open–emitter outputs that allow use as an
inverting/ non–inverting translator or as a differential line driver.
When the common strobe input is at the low logic level, it forces all
true outputs to a MECL low logic state and all inverting outputs to a
MECL high logic state.
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels
are standard or Schottky TTL in, MECL 10,000 out.
An advantage of this device is that TTL level information can be
transmitted differentially, via balanced twisted pair lines, to the MECL
equipment, where the signal can be received by the MC10115 or
MC10116 differential line receivers. The MC10124 is useful in
computers, instrumentation, peripheral controllers, test equipment,
and digital communications systems.
P
D = 380 mW typ/pkg (No Load)
t
pd = 3.5 ns typ (+ 1.5 Vdc in to 50% out)
t
r, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
Gnd
=
PIN 16
VCC (+5.0Vdc) =
PIN 9
VEE (-5.2Vdc) =
PIN 8
11
13
14
10
12
15
7
3
1
6
5
4
2
DIP PIN ASSIGNMENT
BOUT
AOUT
BOUT
AOUT
AIN
COMMON
STROBE
BIN
VEE
GND
COUT
DOUT
DOUT
COUT
DIN
CIN
VCC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10124L
CDIP–16
25 Units / Rail
MC10124P
PDIP–16
25 Units / Rail
MC10124FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10124L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10124
AWLYYWW
1
1
16
MC10124P
AWLYYWW


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