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FSTUD32450 Datenblatt(PDF) 10 Page - Fairchild Semiconductor

Teilenummer FSTUD32450
Bauteilbeschribung  Configurable 4-Bit to 40-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FSTUD32450 Datenblatt(HTML) 10 Page - Fairchild Semiconductor

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10
AC Electrical Characteristics
Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
AC Electrical Characteristics: Translating Diode
Note 10: This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of the typical
On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 11)
Note 11: TA
25qC, f 1 MHz, Capacitance is characterized but not tested.
Symbol
Parameter
TA 40 qC to 85 qC,
Units
CL 50pF, RU RD 500:
Conditions
Figure
VCC 4.5 – 5.5V
VCC 4.0V
(S2 S5 0V)
Number
Min
Max
Min
Max
tPHL, tPLH
Propagation Delay Bus-to-Bus
(Note 9)
0.25
0.25
ns
VI OPEN
Figures
2, 3
tPZH, tPZL
Output Enable Time
1.5
6.5
7.0
ns
VI 7V for tPZL
Figures
2, 3
VI OPEN for tPZH
tPHZ, tPLZ
Output Disable Time
1.5
6.7
7.2
ns
VI 7V for tPLZ
Figures
2, 3
VI OPEN for tPHZ
tPZH, tPZL
Sel (S0, 1) to Output Enable Time
1.5
7.0
7.5
ns
VI 7V for tPZL
Figures
2, 3
VI OPEN for tPZH
tPHZ, tPLZ
Sel (S0, 1) to Output Disable Time
1.5
7.5
7.7
ns
VI 7V for tPLZ
Figures
2, 3
VI OPEN for tPHZ
Symbol
Parameter
TA 40 qC to 85 qC,
Units
CL 50pF, RU RD 500:
Conditions
Figure
VCC 4.5 – 5.5V
(S2 S5 VCC)
Number
Min
Max
tPHL, tPLH
Propagation Delay Bus-to-Bus (Note
10)
0.25
ns
VI OPEN
Figures
2, 3
tPZH, tPZL
Output Enable Time
1.5
10.0
ns
VI 7V for tPZL
Figures
2, 3
VI OPEN for tPZH
tPHZ, tPLZ
Output Disable Time
1.5
9.0
ns
VI 7V for tPLZ
Figures
2, 3
VI OPEN for tPHZ
tPZH, tPZL
Sel (S0, 1) to Output Enable Time
1.5
11.0
ns
VI 7V for tPZL
Figures
2, 3
VI OPEN for tPZH
tPHZ, tPLZ
Sel (S0, 1) to Output Disable Time
1.5
10.0
ns
VI 7V for tPLZ
Figures
2, 3
VI OPEN for tPHZ
Symbol
Parameter
Typ
Max
Units
Conditions
CIN
Control Pin Input Capacitance
4
pF
VCC 5.0V, VIN 0V
CI/O
Input/Output Capacitance “OFF State”
8pF
VCC, OE 5.0V, VIN 0V


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