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4

IRLR8503PbF

Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that

period.

Table 3 – Control FET Losses

Table 4 – Synchronous FET Losses

Conduction

Loss

Gate Drive

Loss

Switching

Loss

Output

Loss

Losses associated with the Q

FET turns on. Losses are caused by both FETs, but are dissipated by the control

FET.

Segment Losses

Description

Losses associated with MOSFET on time. I

current and duty cycle.

Losses associated with charging and discharging the gate of the

MOSFET every cycle. Use the control FET Q

Losses during the drain voltage and drain current transitions for every full cycle.

Losses occur during the Q

Q

)

on

(

DS

RMS

COND

R

I

P

×

=

2

ƒ

×

×

=

G

G

IN

Q

V

P

ƒ

×

×

≈

ƒ

×

×

×

≈

ƒ

×

×

×

≈

G

SW

L

IN

SWITCH

G

GD

L

IN

QGD

G

GS

L

IN

QGS

I

Q

I

V

P

I

Q

I

V

P

I

Q

I

V

P

2

2

F

V

2

Q

P

IN

OSS

OUTPUT

×

×

=

Conduction

Loss

Gate Drive

Loss

Switching

Loss

Output

Loss

Segment Losses

Description

Losses associated with MOSFET on time. I

duty cycle.

Losses associated with charging and discharging the gate of the MOSFET every

cycle. Use the Sync FET Q

Generally small enough to ignore except at light loads when the current reverses

in the output inductor. Under these conditions various light load power saving

techniques are employed by the control IC to maintain switching losses to a

negligible level.

Losses associated with the Q

turns on. They are caused by the synchronous FET, but are dissipated in the control

FET.

DSon

RMS

COND

R

I

P

×

=

2

ƒ

×

×

=

G

G

IN

Q

V

P

0

P

ƒ

×

×

=

IN

OSS

OUTPUT

V

Q

P

2

Figure 7

. 2 & 3-FET solution for

Synchronous Buck Topology.

IRLR8503

Control FET (Q1)

1 x IRLR8103 or

2 x IRLR8503

Synchronous

FET (Q2)

Typical PC Application

The IRLR8103V and the IRLR8503 are suitable for

Synchronous Buck DC-DC Converters, and are optimized

for use in next generation CPU applications. The

IRLR8103V is primarily optimized for use as the low side

synchronous FET (Q2) with low R

immunity.The IRLR8503 is primarily optimized for use as

the high side control FET (Q2) with low cobmined Qsw and

R

IRLR8503 is also tested for Cdv/dt immunity, critical for

the low side socket. The typical configuration in which

these devices may be used in shown in Figure 7.

V

or