Datenblatt-Suchmaschine für elektronische Bauteile |
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YSS940 Datenblatt(PDF) 11 Page - YAMAHA CORPORATION |
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YSS940 Datenblatt(HTML) 11 Page - YAMAHA CORPORATION |
11 / 34 page YSS944/943/940 11 • Audio interface - Master clock, bit clock, word clock, and four serial data (8ch) for input and output are provided respectively. - Various audio interface formats are supported. - The bit clock rate is fixed to 64 fs. - Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz, and 192 kHz. - The bit clock and word clock on the output side have switchable input/output, and can therefore be used as either master or slave. - A clock divider/switching function is included to enable adjustment of the input/output sampling frequency for DTS 96/24, etc. • Audio data output channel control - Audio output data can be output to any of the channels for the SDO3 to SDO0 pins. • Bypass - Output of SDI data to SDO can bypass the internal core logic. • User mute - Output channels can be muted via the microprocessor interface. • External memory interface - Up to 4 Mb of SRAM can be connected for input delay and/or output delay. - Access time can be adjusted via register settings. • Input delay (lip sync) - Input delay for adjusting synchronization between video and audio can be implemented when using external memory. • Output delay - 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 192 kHz can be implemented without using external memory (some exceptions). - 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 96 kHz can be implemented using external memory. • Stream detection - Encoding format detection - Zero detection - Input sampling frequency detection • Auto mute - All channels are muted automatically by detection of noise generation factor. • Status ports - Consecutive-zero data input detection: 1 pin. - Auto mute period output: 1 pin. - Interrupt request output: 1 pin. • General purpose I/O port - 8 general purpose I/O ports are available. - Input and output mode can be switched by register setting. • Internal operating clock generation - Generates the high-speed internal operating clock by on-chip PLL. • Power-up/power-down - Enables power-up/power-down control of the LSI via register settings. |
Ähnliche Teilenummer - YSS940 |
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Ähnliche Beschreibung - YSS940 |
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