74LV86D datasheet(6/15 Pages) NXP

Teilenummer	74LV86D

Bauteilbeschribung	Quad 2-input exclusive-OR gate

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74LV86_3

Product data sheet

Rev. 03 — 27 November 2007

6 of 15

NXP Semiconductors

74LV86

Quad 2-input exclusive-OR gate

10. Dynamic characteristics

[1]

All typical values are measured at Tamb =25 °C.

[2]

tpd is the same as tPLH and tPHL.

[3]

Typical values are measured at nominal supply voltage (VCC = 3.3 V).

[4]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz, fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in V

N = number of inputs switching

Σ(C

L × VCC

2

× f

o) = sum of the outputs.

Table 7.

Dynamic characteristics

GND = 0 V; For test circuit see Figure 7.

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

tpd

propagation delay

nA, nB to nY; see Figure 6

[2]

VCC = 1.2 V

-

70

-

ns

VCC = 2.0 V

-

24

32

-

41

ns

VCC = 2.7 V

-

18

24

-

30

ns

VCC = 3.0 V to 3.6 V; CL =15pF

[3]

-11

-

ns

VCC = 3.0 V to 3.6 V

[3]

-

13

19

-

24

ns

VCC = 4.5 V to 5.5 V

-

16

-

20

ns

CPD

power dissipation

capacitance

CL = 50 pF; fi = 1 MHz;

VI = GND to VCC

[4]

-30

-

pF

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