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SM5921A Datenblatt(PDF) 10 Page - Nippon Precision Circuits Inc

Teilenummer SM5921A
Bauteilbeschribung  8-channel Lip Sync Delay
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Hersteller  NPC [Nippon Precision Circuits Inc]
Direct Link  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5921A Datenblatt(HTML) 10 Page - Nippon Precision Circuits Inc

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SM5921A
SEIKO NPC CORPORATION —10
FUNCTIONAL DESCRIPTION
Delay Settings
The SM5921A sets the delay value set using an MCU interface and adds that delay to the input data. The total
delay value for each channel data is given by the following equation.
nSample-system:
Number of system delay samples (fixed 2 samples)
nSample-intrinsic:
Number of intrinsic delay samples (16-sample units)
nSample-individual:
Number of individual delay samples (1-sample units)
nMp:
Address shift coefficient
fs:
Sampling frequency
Note that even when the intrinsic delay and individual delay are both set to 0 samples, a 2-sample delay is
applied.
Address shift coefficient
The address shift coefficient is determined by the settings of the MP0N and MP1N flags. These enable the time
delay to be multiplied by
×1, ×2, or ×4 without changing the delay value setting. For example, if the sampling
frequency fs is switched from 48kHz to 192kHz and the address shift is set to
×4, then the same delay time is
added.
I
Data setting values cannot exceed the upper limit.
I
Calculation examples
• If fs = 48kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 1, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048)
× 1) ÷ 48000 = 213.3ms
• If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 1, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048)
× 1) ÷ 192000 = 53.3ms
• If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 2, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048)
× 2) ÷ 192000 = 106.6ms
• If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 4, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048)
× 4) ÷ 192000 = 213.3ms
From the examples, it can be seen that switching the sampling frequency from 48kHz to 192kHz and changing
nMp from 1 to 4 results in an identical time delay. Note, however, that the memory size physical limit cannot
be exceeded. So, for example, the physical limit is reached with a sum (nSample-intrinsic + nSample-individ-
ual) of 16384 samples when nMp = 4, or the equivalent of 65535 samples at nMp = 1.
MP0N
MP1N
nMp
LOW
LOW
1
LOW
HIGH
2
HIGH
LOW
4
HIGH
HIGH
1
t
Delay
sec
()
nSample-system
nSample-intrinsic
nSample-individual
+
() nMp
×
+
()
fs
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=


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