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MCZ33927EK Datenblatt(PDF) 3 Page - Freescale Semiconductor, Inc |
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MCZ33927EK Datenblatt(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 44 page Analog Integrated Circuit Device Data Freescale Semiconductor 3 33927 PIN CONNECTIONS PIN CONNECTIONS Figure 3. 33927 Pin Connections Table 1. 33927 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 20. Pin Pin Name Pin Function Formal Name Definition 1 PHASEA Digital Output Phase A Totem Pole output of Phase A comparator. This output is low when the voltage on PA_HS_S (Source of High-Side FET) is less than 50% of VBAT 2 PGND Ground Power Ground Power ground for charge pump 3 EN1 Digital Input Enable 1 Logic signal input must be high (ANDed with EN2) to enable any gate drive output. 4 EN2 Digital Input Enable 2 Logic signal input must be high (ANDed with EN1) to enable any gate drive output 5 RST Digital Input Reset Reset input 6, 33, 49, 50, 52, 53 N/C – No Connect These pins do not connect 7 PUMP Power Drive Out Pump Charge pump output 8 VPUMP Power Input Voltage Pump Charge pump supply 9 VBAT Digital Input Voltage Battery Battery supply 10 PHASEB Digital Output Phase B Totem Pole output of Phase B comparator. This output is low when the voltage on PB_HS_S (Source of High-Side FET) is less than 50% of VBAT 11 PHASEC Digital Output Phase C Totem Pole output of Phase C comparator. This output is low when the voltage on PC_HS_S (Source of High-Side FET) is less than 50% of VBAT 54 40 .35 34 33 32 31 30 29 28 39 38 37 36 47 46 45 44 43 42 41 51 50 49 48 53 52 1 15 20 21 22 23 24 25 26 27 16 17 18 19 8 9 10 11 12 13 14 4 5 6 7 2 3 PHASEA PGND EN1 EN2 RST N/C PUMP VPUMP VBAT PHASEB PHASEC PA_HS PA_LS VDD PB_HS PB_LS INT CS SI SCLK SO PC_LS PC_HS AMP_OUT AMP_N AMP_P OC_OUT VPWR N/C N/C VLS N/C N/C PA_BOOT PA_HS_G PA_HS_S PA_LS_G PGNDA PB_BOOT PB_HS_G PB_HS_S PB_LS_G PGNDB PC_BOOT PC_HS_G PC_HS_S PC_LS_G PGNDC N/C VLS_CAP GND1 GND0 VSS OC_TH |
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