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TMPR4937XBG-300 Datenblatt(PDF) 6 Page - Toshiba Semiconductor |
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TMPR4937XBG-300 Datenblatt(HTML) 6 Page - Toshiba Semiconductor |
6 / 552 page Table of Contents ii 6.2.2 Power Reduction for Peripheral Modules............................................................................................ 6-5 6.3 Power-On Sequence ....................................................................................................................................... 6-6 7. External Bus Controller .......................................................................................................................................... 7-1 7.1 Features .......................................................................................................................................................... 7-1 7.2 Block Diagram ............................................................................................................................................... 7-2 7.3 Detailed Explanation...................................................................................................................................... 7-3 7.3.1 External Bus Control Register ............................................................................................................. 7-3 7.3.2 Global/Boot-up Options....................................................................................................................... 7-4 7.3.3 Address Mapping................................................................................................................................. 7-5 7.3.4 External Address Output ...................................................................................................................... 7-6 7.3.5 Data Bus Size....................................................................................................................................... 7-7 7.3.6 Access Mode........................................................................................................................................ 7-9 7.3.7 Access Timing ................................................................................................................................... 7-13 7.3.8 Clock Options .................................................................................................................................... 7-19 7.4 Register ........................................................................................................................................................ 7-20 7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7)...... 7-21 7.5 Timing Diagrams ......................................................................................................................................... 7-24 7.5.1 ACE* Signal ...................................................................................................................................... 7-25 7.5.2 Normal mode access (Single, 32-bit Bus).......................................................................................... 7-27 7.5.3 Normal mode access (Burst, 32-bit Bus) ........................................................................................... 7-31 7.5.4 Normal Mode Access (Single, 16-bit bus) .........................................................................................7-33 7.5.5 Normal Mode Access (Burst, 16-bit Bus) ..........................................................................................7-37 7.5.6 Normal Mode Access (Single, 8-bit Bus) ..........................................................................................7-39 7.5.7 Normal Mode Access (Burst, 8-bit Bus) ............................................................................................ 7-42 7.5.8 Page Mode Access (Burst, 32-bit Bus) .............................................................................................. 7-44 7.5.9 External ACK Mode Access (32-bit Bus) .......................................................................................... 7-46 7.5.10 READY Mode Access (32-bit Bus) ................................................................................................... 7-52 7.6 Flash ROM, SRAM Usage Example ........................................................................................................... 7-54 8. DMA Controller...................................................................................................................................................... 8-1 8.1 Features .......................................................................................................................................................... 8-1 8.2 Block Diagram ............................................................................................................................................... 8-2 8.3 Detailed Explanation...................................................................................................................................... 8-4 8.3.1 Transfer Mode...................................................................................................................................... 8-4 8.3.2 On-chip Registers ................................................................................................................................ 8-5 8.3.3 External I/O DMA Transfer Mode ....................................................................................................... 8-5 8.3.4 Internal I/O DMA Transfer Mode ........................................................................................................ 8-8 8.3.5 Memory-Memory Copy Mode............................................................................................................. 8-9 8.3.6 Memory Fill Transfer Mode ................................................................................................................ 8-9 8.3.7 Single Address Transfer ....................................................................................................................... 8-9 8.3.8 Dual Address Transfer ....................................................................................................................... 8-12 8.3.9 DMA Transfer .................................................................................................................................... 8-17 8.3.10 Chain DMA Transfer ......................................................................................................................... 8-18 8.3.11 Dynamic Chain Operation ................................................................................................................. 8-20 8.3.12 Interrupts............................................................................................................................................ 8-21 8.3.13 Transfer Stall Detection Function ...................................................................................................... 8-21 8.3.14 Arbitration Among DMA Channels ................................................................................................... 8-22 8.3.15 Restrictions in Access to PCI Bus...................................................................................................... 8-22 8.4 DMA Controller Registers ........................................................................................................................... 8-23 8.4.1 DMA Master Control Register (DM0MCR, DM1MCR)................................................................... 8-25 8.4.2 DMA Channel Control Register (DM0CCRn, DM1CCRn) .............................................................. 8-27 8.4.3 DMA Channel Status Register (DM0CSRn, DM1CSRn)) ................................................................ 8-31 8.4.4 DMA Source Address Register (DM0SARn, DM1SARn) ................................................................ 8-33 8.4.5 DMA Destination Address Register (DM0DARn, DM1DARn)........................................................ 8-34 8.4.6 DMA Chain Address Register (DM0CHARn, DM1CHARn) ........................................................... 8-35 8.4.7 DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)............................................. 8-36 |
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