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MC14526B Datenblatt(PDF) 1 Page - Motorola, Inc |
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MC14526B Datenblatt(HTML) 1 Page - Motorola, Inc |
1 / 10 page MOTOROLA CMOS LOGIC DATA 1 MC14522B MC14526B Presettable 4-Bit Down Counters The MC14522B BCD counter and the MC14526B binary counter are constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. These devices are presettable, cascadable, synchronous down counters with a decoded “0” state output for divide–by–N applications. In single stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide–by–N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. These complementary MOS counters can be used in frequency synthesiz- ers, phase–locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge–Clocked Design — Incremented on Positive Transition of Clock or Negative Transition of Inhibit • Asynchronous Preset Enable • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C FUNCTION TABLE Inputs Output Resulting Function Clock Reset Inhibit Preset Enable Cascade Feedback “0” Resulting Function X X X H H H X X X L H X L L H L H H Asynchronous reset* Asynchronous reset Asynchronous reset X X X H H H X X X L H X L L H L H H Asynchronous reset* Asynchronous reset Asynchronous reset X H X X H H Asynchronous reset X L X H X L Asynchronous preset L L L H L L X X L L Decrement inhibited Decrement inhibited L L L X L Decrement inhibited H H L L L L L L L L L L L L L L L L L No change** (inactive edge) No change** (inactive edge) Decrement** Decrement** H L L L L L L L L L L L L L L L L L L No change** (inactive edge) No change** (inactive edge) Decrement** Decrement** H L L L L L L L L L Decrement** Decrement** H L L L L Decrement** X = Don’t Care NOTES: * Output “0” is low when reset goes high only it PE and CF are low. ** Output “0” is high when reset is low, only if CF is high and count is 0000. MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14522B MC14526B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBDW SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, pre- cautions must be taken to avoid applications of any voltage higher than maximum rated volt- ages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. PIN ASSIGNMENT 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 “0” CF P2 Q2 VDD Q1 RESET P1 INHIBIT PE P3 Q3 VSS Q0 CLOCK P0 |
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