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74AHCT573PW Datenblatt(PDF) 2 Page - NXP Semiconductors

Teilenummer 74AHCT573PW
Bauteilbeschribung  Octal D-type transparent latch; 3-state
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AHCT573PW Datenblatt(HTML) 2 Page - NXP Semiconductors

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2003 Dec 08
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC573; 74AHCT573
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Common 3-state output enable input
• Functionally identical to the 74AHC/AHCT563 and
74AHC/AHCT373
• Inputs accepts voltages higher than VCC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT573 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT573 are octal D-type transparent
latches featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are
common to all latches.
The 74AHC/AHCT573 consists of eight D-type transparent
latches with 3-state true outputs. When pin LE is HIGH,
data at the Dn inputs enters the latches. In this condition
the latches are transparent, i.e. a latch output will change
state each time its corresponding D-input changes.
When pin LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When pin OE is LOW, the
contents of the 8 latches are available at the outputs.
When pin OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input
does not affect the state of the latches.
The 74AHC/AHCT573 is functionally identical to the
74AHC/AHCT533, 74AHC/AHCT563 and
74AHC/AHCT373, but the 74AHC/AHCT533 and
74AHC/AHCT563 have inverted outputs and the
74AHC/AHCT563 and 74AHC/AHCT373 have a different
pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay Dn to Qn;
LE to Qn
CL = 15 pF; VCC = 5 V
3.9
3.5
ns
CI
input capacitance
VI =VCC or GND
3.0
3.0
pF
CO
output capacitance
4.0
4.0
pF
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
12
18
pF


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