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S-1112B24PI-L6JTFG Datenblatt(PDF) 11 Page - Seiko Instruments Inc |
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S-1112B24PI-L6JTFG Datenblatt(HTML) 11 Page - Seiko Instruments Inc |
11 / 30 page HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR Rev.5.1_00 S-1112/1122 Series Seiko Instruments Inc. 11 Standard Circuit ON/OFF VSS VOUT VIN CIN *1 CL *2 Input Output GND Single GND *1. CIN is a capacitor for stabilizing the input. *2. A ceramic capacitor of 0.47 µF or more can be used for CL. Figure 10 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. Application Conditions Input capacitor (CIN): 1.0 µF or more Output capacitor (CL): 0.47 µF or more ESR of output capacitor: 10 Ω or less Caution A general series regulator may oscillate, depending on the external components selected. Check that no oscillation occurs with the application using the above capacitor. |
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