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OP297 Datenblatt(PDF) 4 Page - Analog Devices

Teilenummer OP297
Bauteilbeschribung  Dual Low Bias Current Precision Operational Amplifier
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OP297
Rev. F | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltage
±20 V
Input Voltage
±20 V
1
Differential Input Voltage
40 V
1
Output Short-Circuit Duration
Indefinite
Storage Temperature Range
Z Package
−65°C to +175°C
P, S Packages
−65°C to +150°C
THERMAL RESISTANCE
Operating Temperature Range
OP297E (Z)
−40°C to +85°C
θ is specified for worst-case mounting conditions, that is, θ
JA
JA
is specified for device in socket for CERDIP and PDIP pack-
ages; θ
OP297F, OP297G (P, S)
−40°C to +85°C
Junction Temperature
JA
is specified for device soldered to printed circuit board
for the SOIC package.
Z Package
−65°C to +175°C
P, S Packages
−65°C to +150°C
Table 4. Thermal Resistance
300°C
Lead Temperature
(Soldering, 60 sec)
Package Type
θ
θ
Unit
JA
JC
8-Lead CERDIP (Z-Suffix)
134
12
°C/W
1 For supply voltages less than ±20 V, the absolute maximum input voltage is
equal to the supply voltage.
8-Lead PDIP (P-Suffix)
96
37
°C/W
8-Lead SOIC (S-Suffix)
150
41
°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
+
1/2
OP297
+
1/2
OP297
50kΩ
50Ω
2kΩ
V1 20V p-p @ 10Hz
V2
CHANNEL SEPARATION = 20 log
V1
V2/10000
Figure 4. Channel Separation Test Circuit


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