DS1302 Trickle-Charge Timekeeping Chip

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COMMAND BYTE

Figure 4 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic

1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1.

Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation

(input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).

Figure 4. Address/Command Byte

CE AND CLOCK CONTROL

Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the

control logic that allows access to the shift register for the address/command sequence. Second, the CE signal

provides a method of terminating either single-byte or multiple-byte CE data transfer.

A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during

the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data

transfer terminates and the I/O pin goes to a high-impedance state. Figure 5 shows data transfer. At power-up, CE

DATA INPUT

Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next

eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with

bit 0.

DATA OUTPUT

Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the

next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit

of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur

so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri-

stated upon each rising edge of SCLK. Data is output starting with bit 0.

BURST MODE

Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal

(address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or

write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in

the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.

When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to

be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to

transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not.

CLOCK/CALENDAR

The time and calendar information is obtained by reading the appropriate register bytes. Table 2 illustrates the RTC

registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the

time and calendar registers are in the binary-coded decimal (BCD) format.

1

RAM

CK

A4

A3

A2

A1

A0

RD

WR

7654

3210