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AD1888JSTZ Datenblatt(PDF) 6 Page - Analog Devices |
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AD1888JSTZ Datenblatt(HTML) 6 Page - Analog Devices |
6 / 32 page AD1888 Rev. A | Page 6 of 32 TIMING PARAMETERS Guaranteed over operating temperature range. Table 2. Parameter Symbol Min Typ Max Unit RESET Active Low Pulse Width tRST_LOW 1.0 μs RESET Inactive to BIT_CLK Startup Delay tRST2CLK 162.8 400,000 ns SYNC Active High Pulse Width tSYNC_HIGH 1.3 μs SYNC Low Pulse Width tSYNC_LOW 19.5 μs SYNC Inactive to BIT_CLK Startup Delay tSYNC2CLK 162.8 ns BIT_CLK Frequency 12.288 MHz BIT_CLK Frequency Accuracy ±1.0 ppm BIT_CLK Period tCLK_PERIOD 81.4 ns BIT_CLK Output Jitter1, 2 750 ps BIT_CLK High Pulse Width tCLK_HIGH 40 41.7 ns BIT_CLK Low Pulse Width tCLK_LOW 39.7 41.4 ns SYNC Frequency 48.0 kHz SYNC Period tSYNC_PERIOD 20.8 μs Setup to Falling Edge of BIT_CLK tSETUP 4 ns Hold from Falling Edge of BIT_CLK tHOLD 3 ns BIT_CLK Rise Time tRISECLK 2 4 6 ns BIT_CLK Fall Time tFALLCLK 2 4 6 ns SYNC Rise Time tRISESYNC 2 4 6 ns SYNC Fall Time tFALLSYNC 2 4 6 ns SDATA_IN Rise Time tRISEDIN 2 4 6 ns SDATA_IN Fall Time tFALLDIN 2 4 6 ns SDATA_OUT Rise Time tRISEDOUT 2 4 6 ns SDATA_OUT Fall Time tFALLDOUT 2 4 6 ns End of Slot 2 to BIT_CLK, SDATA_IN Low tS2_PDOWN 0 1.0 μs Setup to RESET Inactive (SYNC, SDATA_OUT) tSETUP2RST 15 ns Rising Edge of RESET to Hi-Z Delay tOFF 25 ns Propagation Delay 15 ns RESET Rise Time 50 ns Output Valid Delay from BIT_CLK Rising 15 ns 1 Guaranteed but not tested. 2 Output jitter directly dependent on crystal input jitter. RESET BIT_CLK SDATA_IN tRST_LOW tRST2CLK tTRI2ACTV tTRI2ACTV Figure 2. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal) SYNC BIT_CLK tSYNC_HIGH tSYNC2CLK Figure 3. Warm Reset Timing |
Ähnliche Teilenummer - AD1888JSTZ |
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Ähnliche Beschreibung - AD1888JSTZ |
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