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M41T256Y Datenblatt(PDF) 9 Page - STMicroelectronics |
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M41T256Y Datenblatt(HTML) 9 Page - STMicroelectronics |
9 / 27 page 9/27 M41T256Y READ Mode In this mode the master reads the M41T256Y slave after setting the slave address (see Figure 10., page 9). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the byte ad- dresses A(0) and A(1) are written to the on-chip address pointer (MSB of address byte A(0) is a “Don’t care”). Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master trans- mitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Figure 11., page 10). Note: Address pointer will wrap around from max- imum address to minimum address if consecutive READ or WRITE cycles are performed. An alternate READ Mode may also be implement- ed whereby the master reads the M41T256Y slave without first writing to the (volatile) address point- er. The first address that is read is the last one stored in the pointer (see Figure 12., page 10). Figure 10. Slave Address Location Note: The most significant bit is sent first. AI00602 R/W SLAVE ADDRESS START A 0 100 0 11 |
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