M41T256YMH7F datasheet(6/27 Pages) STMICROELECTRONICS

Teilenummer	M41T256YMH7F

Bauteilbeschribung	256 Kbit 32K x8 SERIAL RTC

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M41T256Y

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OPERATING MODES

The M41T256Y clock operates as a slave device

on the serial bus. Access is obtained by imple-

menting a start condition followed by the correct

slave address (D0h). The 256K bytes contained in

the device can then be accessed sequentially in

the following order:

0-7FEF = General Purpose RAM

7FF0-7FF6 = Reserved

7FF7h = Tenths/Hundredths Register

7FF8h = Control Register

7FF9h = Seconds Register

7FFAh = Minutes Register

7FFBh = Hour Register

7FFCh = Tamper/Day Register

7FFDh = Date Register

7FFEh = Month Register

7FFFh = Year Register

The M41T256Y clock continually monitors VCC for

an out-of tolerance condition. Should VCC fall be-

low VPFD, the device terminates an access in

progress and resets the device address counter.

Inputs to the device will not be recognized at this

time to prevent erroneous data from being written

to the device from an out-of-tolerance system.

When VCC falls below VSO, the device automati-

cally switches over to the battery and powers

down into an ultra low current mode of operation to

conserve battery life. As system power returns and

VCC rises above VSO, the battery is disconnected,

and the power supply is switched to external VCC.

Write protection continues until VCC reaches VPFD

plus tREC.

For more information on Battery Storage Life refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines must be connected to

a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the bus

is not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

High, will be interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in the state of the

data line, from High to Low, while the clock is High,

defines the START condition.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition.

Data Valid. The state of the data line represents

valid data when after a start condition, the data line

is stable for the duration of the high period of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condition

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each receiver acknowl-

edges with a ninth bit.

By definition a device that gives out a message is

called “transmitter,” the receiving device that gets

the message is called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by the master are called

“slaves.”

Acknowledge. Each byte of eight bits is followed

by one acknowledge clock pulse. This acknowl-

edge clock pulse is a low level put on the bus by

the receiver whereas the master generates an ex-

tra acknowledge related clock pulse. A slave re-

ceiver which is addressed is obliged to generate

an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken into account. A master receiver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case the

transmitter must leave the data line High to enable

the master to generate the STOP condition.

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