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M40Z300WMQ1TR Datenblatt(PDF) 3 Page - STMicroelectronics |
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M40Z300WMQ1TR Datenblatt(HTML) 3 Page - STMicroelectronics |
3 / 16 page 3/16 M40Z300, M40Z300W Table 2. Absolute Maximum Ratings (1) Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. Symbol Parameter Value Unit TA Ambient Operating Temperature 0 to 70 °C TSTG Storage Temperature (VCC Off) SNAPHAT SOIC –40 to 85 –55 to 125 °C VIO Input or Output Voltages –0.3 to VCC +0.3 V VCC Supply Voltage M40Z300 M40Z300W –0.3 to 7 –0.3 to 4.6 V IO Output Current 20 mA PD Power Dissipation 1 W OPERATION The M40Z300/W, as shown in Figure 4, can con- trol up to four (eight, if placed in parallel) standard low-power SRAMs. These SRAMs must be config- ured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E1CON to E4CON ) output pins follow the chip enable (E) input pin with timing shown in Table 7. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). When VCC degrades during a power failure, E1CON to E4CON are forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-toler- ance threshold (VPFD). For the M40Z300 the pow- er fail detection value associated with VPFD is selected by the Threshold Select (THS) pin and is shown in Table 6A. For the M40Z300W, the THS pin selects both the supply voltage and VPFD as shown in Table 6B. Note: In either case, THS pin must be connected to either VSS or VOUT. If chip enable access is in progress during a power fail detection, that memory cycle continues to com- pletion before the memory is write protected. If the memory cycle is not terminated within time tWPT, E1CON to E4CON are unconditionally driven high, write protecting the SRAM. A power failure during a write cycle may corrupt data at the currently ad- dressed location, but does not jeopardize the rest of the SRAM’s contents. At voltages below VPFD (min), the user can be assured the memory will be write protected within the Write Protect Time (tWPT) provided the VCC fall time exceeds tF (See Table 7). As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery provides a volt- age VOHB to the SRAM and can supply current IOUT2 (see Table 6A/6B). When VCC rises above VSO, VOUT is switched back to the supply voltage. Outputs E1CON to E4CON are held inactive for tCER (120ms maxi- mum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 6). |
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