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UPA to PCI Interface
U2P
STP2223BGA
July 1997
Typical System Partition
Figure 1. shows one possible configuration of U2P in a PCI UltraSPARC system. U2P connects to the System
Controller chip and other UPA ports via UPA address, control and data busses. The system has both PCI and
EPCI slots, as well as an on board PCI device (PCIO). Interrupt information is provided by the RIC chip, and
a JTAG port is provided for board testing as well as in-circuit testing and debugging of U2P.
Figure 1. Typical System Block Diagram
Ultra
UDB
Tag
512KB
E$
Clk
TA(15:0)
TD(24+3+P)
DA(18+16BE)
D(128+16P)
Graphics
System
Memory SIMMs
Memory Address
Memory Control
Memory Data (256+32ECC)
BMX
UPA_A0(35:0)
UPA_A1(35:0)
UPA_D0(127:0+ECC)
UPA_D1(63:0+ECC)
UPA_Ctrl
U2P
UPA Interface
PCI Interface A
PCI Interface B
PCI Bus
PCI Bus
RIC
Controller
SPARC
Bus
Adapter
PCIO