MV20556

MOSEL VITELIC INC.

10/27

PID256** 07/97

Specifications subject to change without notice, contact your sales representatives for the most recent information.

Preliminary

Interrupt System(Cont'd)

Interrupt System Functional Description (Cont'd)

high or low by the polarity of a bit in the Interrupt

Priority register. These bit assignments are shown in

IP definition. Setting the resource's associated bit to a

one (1) programs it to the higher level. The priority of

multiple interrupt requests occurring simultaneously

and assigned to the same priority level is also shown in

below table.

The servicing of a resources's interrupt request occurs

at the end of the instruction-in-progress. The processor

transfers control to the starting address of this

resource's interrupt service program and begins

execution.

Within the Interrupt Enable register (IE)

there are six addressable flags.

Five flags

enable/disable the five interrupt sources when

set/cleared. Setting/clearing the sixth flag permits a

global enable/disable of each enabled interrupt request.

Setting/clearing a bit in the Interrupt Priority register

(IP) establishes its associated interrupt request as a

high/low priority (Table on next page). If a low-priority

level interrupt is being serviced, a high-priority level

interrupt will interrupt it. However, an interrupt source

cannot interrupt a service program of the same or

higher level.

The processor records the active priority level(s) by

setting

internal

flip-flop(s).

One

of

these

non-addressable flip-flops is set while a low-level

interrupt is being serviced. The other flip-flop is set

while the high-level interrupt is being serviced. The

appropriate flip-flop is set when the processor transfers

control to the service program.

The flip-flop

corresponding to the interrupt level being serviced is

reset when the processor executes an RETI Instruction.

To summarize, the sequence of events for an interrupt

is: A resource provokes an interrupt by setting its

associated interrupt request bit to let the processor

know an interrupt condition has occurred. The CPU's

internal hardware latches the interrupt request near the

falling-edge of ALE internal signal in the tenth (10th),

twenty-second (22nd), thirty-fourth (34th) and forty-six

(46th) oscillator period of the instruction-in-progress.

The interrupt request is conditioned by bits in the

interrupt enable and interrupt priority registers.

The

processor acknowledges the interrupt by setting one of

the two internal "priority-level active" flip-flops and

performing a hardware subroutine call. The call pushes

the PC (but not the PSW) onto the stack and, for most

sources, clears the interrupt request flag. The service

program is then executed. Control is returned to the

main program when the RETI instruction is executed.

The RETI instruction also clears one of the internal

"priority-level active" flip-flops.

Most interrupt request flags (IE0, IE1, TF0 and TF1)

are cleared when the processor transfers control to the

first instruction of the interrupt service program. The TI

and RI interrupt request flags are the exceptions and

must be cleared as part of the serial port's interrupt

service program.

The process whereby a high-level interrupt request

interrupt a low-level interrupt service program is called

nesting. In this case the address of the next instruction

in the low-priority service program is pushed onto the

stack, the stack pointer is incremented by two (2) and

processor control is transferred to the Program Memory

location of the first instruction of the high-level service

program.

The last instruction of the high-priority

interrupt service program must be an RETI instruction.

This instruction clears the high "priority-level-active"

flip-flop.

RETI also returns processor control to the

next instruction of the low-level interrupt service

program. Since the lower "priority-level-active" flip-flop

has remained set, high priority interrupts are re-enable

while further low priority interrupts remain disabled.

Interrupt Source

Request Flag

IE0

TF0

IE1

TF1

TI

RI

Bit Location

TCON.1

TCON.5

TCON.3

TCON.7

SCON.1

SCON.0

HEX

0003H

000Bh

0013H

001Bh

0023h

External Request 0

Internal timer 0/ counter 0

External request 1

Internal timer 1/ counter 1

Internal Serial Port (Xmit)

Internal Serial Port (Rcvr)

Start address

Priority Flags

.0 (highest)

.1

.2

.3

.4

(lowest)

Decimal

3

11

19

27

35

Interrupt flags & addresses