Datenblatt-Suchmaschine für elektronische Bauteile |
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LM2507 Datenblatt(PDF) 10 Page - National Semiconductor (TI) |
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LM2507 Datenblatt(HTML) 10 Page - National Semiconductor (TI) |
10 / 22 page Functional Description (Continued) To account for the latency through the MPL link, a dual READ operation is required by the host. The first read re- turns invalid data (all Low), which the host ignores. Once data has returned to the Master, the INTR signal is asserted to inform the host to initiate a second read operation. During this second read operation the MD line is held in the idle bus phase and valid data is returned through the Master device. After the CS* Low-to-High transition the INTR is de- asserted. The use of the INTR pin is optional. The host may simply wait long enough and then issue the 2nd Read to the Master. In this case the INTR MST output should be leaft as a NC (no connect). READ data will be returned by 36 or 46 MC cycles (depending upon IDR setting). The host just need to wait till after the data is ready and then access it (i.e. 50 or more MC cycles). 20186009 FIGURE 10. READ_Data and TA” www.national.com 10 |
Ähnliche Teilenummer - LM2507 |
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Ähnliche Beschreibung - LM2507 |
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