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ST93CS66B3013TR Datenblatt(PDF) 10 Page - STMicroelectronics |
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ST93CS66B3013TR Datenblatt(HTML) 10 Page - STMicroelectronics |
10 / 16 page Accessing the Protect Register is done by execut- ing the following sequence: – WEN: execute the Write Enable instruction, – PREN: execute the PREN instruction, – PRWRITE, PRCLEAR or PRDS: the protection then may be defined, in terms of size of the protected area (PRWRITE, PRCLEAR) and may be set permanently (PRDS instruction). Protect Register Read The Protect Register Read instruction (PRREAD) outputs on the Data Output Q the content of the Protect Register, followed by the Protect Flag bit. The Protect Register Enable pin (PRE) must be driven High before and during the instruction. As in the Read instruction a dummy ’0’ bit is output first. Since it is not possible to distinguish if the Protect Register is cleared (all 1’s) or if it is written with all 1’s, user must check the Protect Flag status (and not the Protect Register content) to ascertain the setting of the memory protection. Protect Register Enable The Protect Register Enable instruction (PREN) is used to authorize the use of further PRCLEAR, PRWRITE and PRDS instructions. The PREN insruction does not modify the Protect Flag bit value. Note: A Write Enable (WEN) instruction must be executed before the Protect Enable instruction. Both the Protect Enable (PRE) and Write Enable (W) input pins must be held High during the instruc- tion execution. Protect Register Clear The Protect Register Clear instruction (PRCLEAR) clears the address stored in the Protect Register to all 1’s, and thus enables the execution of WRITE and WRALL instructions. The Protect Register Clear execution clears the Protect Flag to ’1’. Both the Protect Enable (PRE) and Write Enable (W) input pins must be driven High during the instruc- tion execution. Note: A PREN instruction must immediately pre- cede the PRCLEAR instruction. Protect Register Write The Protect Register Write instruction (PRWRITE) is used to write into the Protect Register the ad- dress of the first word to be protected. After the PRWRITE instruction execution, all memory loca- tions equal to and above the specified address, are protected from writing. The Protect Flag bit is set to ’0’, it can be read with Protect Register Read instruction. Both the Protect Enable (PRE) and Write Enable (W) input pins must be driven High during the instruction execution. Note: A PREN instruction must immediately pre- cede the PRWRITE instruction, but it is not neces- sary to execute first a PRCLEAR. Protect Register Disable The Protect Register Disable instruction sets the One Time Programmable bit (OTP bit). The Protect Register Disable instruction (PRDS) is a ONE TIME ONLY instruction which latches the Protect Regis- ter content, this content is therefore unalterable in the future. Both the Protect Enable(PRE) and Write Enable (W) input pins must be driven High during the instruction execution. The OTP bit cannot be directly read, it can be checked by reading the content of the Protect Register (PRREAD instruc- tion), then by writing this same value into the Pro- tect Register (PRWRITE instruction): when the OTP bit is set, the Ready/Busy status cannot ap- pear on the Data output (Q); when the OTP bit is not set, the Busy status appear on the Data output (Q). A PREN instruction must immediately precede the PRDS instruction. READY/BUSY Status When the ST93CS66/67 is performing the write cycle, the Busy signal (Q = 0) is returned if S is driven high, and the ST93CS66/67 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate, if S is driven high, that the ST93CS66/67 is ready to receive a new instruction. Once the ST93CS66/67 is Ready, the Data Output Q is set to ’1’ until a new Start bit is decoded or the Chip Select is brought Low. COMMON I/O OPERATION The Data Output (Q) and Data Input (D) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. Some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (A0) and the first data bit output by Q. The reader should refer to the SGS-THOMSON application note ”MICROWIRE EEPROM Common I/O Opera- tion”. MEMORY WRITE PROTECTION (cont’d) 10/16 ST93CS66, ST93CS67 |
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