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AD7153BRMZ Datenblatt(PDF) 5 Page - Analog Devices |
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AD7153BRMZ Datenblatt(HTML) 5 Page - Analog Devices |
5 / 24 page AD7152/AD7153 Rev. 0 | Page 5 of 24 TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +85°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SERIAL INTERFACE1, 2 See Figure 3. SCL Frequency 0 400 kHz SCL High Pulse Width, tHIGH 0.6 μs SCL Low Pulse Width, tLOW 1.3 μs SCL, SDA Rise Time, tR 0.3 μs SCL, SDA Fall Time, tF 0.3 μs Hold Time (Start Condition), tHD;STA 0.6 μs After this period, the first clock is generated. Set-Up Time (Start Condition), tSU;STA 0.6 μs Relevant for repeated start condition. Data Set-Up Time, tSU;DAT 0.1 μs Setup Time (Stop Condition), tSU;STO 0.6 μs Data Hold Time, tHD;DAT (Master) 0.01 μs Bus-Free Time (Between Stop and Start Conditions, tBUF) 1.3 μs 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs; output load = 10 pF. P S tLOW tR tF tHD;STA tHD;DAT tSU;DAT tSU;STA tHD;STA tSU;STO tHIGH SCL PS SDA tBUF Figure 3. Serial Interface Timing Diagram |
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