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LC4128ZC-75MN132C Datenblatt(PDF) 2 Page - Lattice Semiconductor |
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LC4128ZC-75MN132C Datenblatt(HTML) 2 Page - Lattice Semiconductor |
2 / 99 page Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 2 Table 2. ispMACH 4000Z Family Selection Guide ispMACH 4000 Introduction The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattice’s two most popular architectures: the ispLSI ® 2000 and ispMACH 4A. Retaining the best of both families, the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family. The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil- ity, routing, pin-out retention and density migration. The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com- binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B) and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/ 2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to VCC (logic core). Overview The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. ispMACH 4032ZC ispMACH 4064ZC ispMACH 4128ZC ispMACH 4256ZC Macrocells 32 64 128 256 I/O + Dedicated Inputs 32+4/32+4 32+4/32+12/ 64+10/64+10 64+10/96+4 64+10/96+6/ 128+4 tPD (ns) 3.5 3.7 4.2 4.5 tS (ns) 2.2 2.5 2.7 2.9 tCO (ns) 3.0 3.2 3.5 3.8 fMAX (MHz) 267 250 220 200 Supply Voltage (V) 1.8 1.8 1.8 1.8 Max. Standby Icc (µA) 20 25 35 55 Pins/Package 48 TQFP 56 csBGA 48 TQFP 56 csBGA 100 TQFP 132 csBGA 100 TQFP 132csBGA 100 TQFP 132 csBGA 176 TQFP |
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