Datenblatt-Suchmaschine für elektronische Bauteile |
|
AD9958BCPZ Datenblatt(PDF) 10 Page - Analog Devices |
|
AD9958BCPZ Datenblatt(HTML) 10 Page - Analog Devices |
10 / 44 page AD9958 Rev. A | Page 10 of 44 Pin No. Mnemonic I/O1 Description 24 CLK_MODE_SEL I Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator section is enabled to accept a crystal as the REF_CLK source. When low, the oscillator section is bypassed. 27 LOOP_FILTER I Connects to the external zero compensation network of the PLL loop filter. Typically, the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD. 28, 32, 34, 38 NC N/A No Connection. 40, 41, 42, 43 P0, P1, P2, P3 I Data pins used for modulation (FSK, PSK, ASK), to start/stop for the sweep accumulators, or used to ramp up/ramp down the output amplitude. The data is synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the setup and hold time requirements to the SYNC_CLK. The functionality of these pins is controlled by profile pin configuration (PPC) bits (FR1[14:12]). 46 I/O_UPDATE I A rising edge transfers data from the serial I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the setup and hold time requirements to the SYNC_CLK to guarantee a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of pipeline uncertainty exists. The minimum pulse width is one SYNC_CLK period. 47 CS I Active Low Chip Select. Allows multiple devices to share a common I/O bus (SPI). 48 SCLK I Serial Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK. 49 DVDD_I/O I 3.3 V Digital Power Supply for SPI Port and Digital I/O. 50 SDIO_0 I/O Data Pin SDIO_0 is dedicated to the serial port I/O only. 51, 52, 53 SDIO_1, SDIO_2, SDIO_3 I/O Data Pin SDIO_1, Data Pin SDIO_2, and Data Pin SDIO_3 can be used for the serial I/O port or used to initiate a ramp-up/ramp-down (RU/RD) of the DAC output amplitude. 54 SYNC_CLK O The SYNC_CLK runs at one fourth the system clock rate. It can be disabled. I/O_UPDATE or data (Pin 40 to Pin 43) is synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE or data (Pin 40 to Pin 43) must meet the setup and hold time requirements to the rising edge of SYNC_CLK; otherwise, a ±1 SYNC_CLK period of uncertainty exists. 1 I = input, O = output. |
Ähnliche Teilenummer - AD9958BCPZ |
|
Ähnliche Beschreibung - AD9958BCPZ |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |