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MC-ACT-VME2416 Datenblatt(PDF) 4 Page - Actel Corporation

Teilenummer MC-ACT-VME2416
Bauteilbeschribung  FlexibleslaveVMEcontroller Fullinterruptcontroller(ROAK
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MC-ACT-VME2416 Datenblatt(HTML) 4 Page - Actel Corporation

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VME2416
Memec Design
February 25, 2003
4
Optimized for
Between the user part and the VME controller, the transfer of interrupt information is based on the
request/acknowledge protocol.
When an interrupt occurs on the user part, it generates an interrupt request on the VME controller through the
signal USER_IREQ. Depending on the value defined by the user part on the vector USER_ILEV, the VME controller
activates an interrupt on the respective interrupt line VME_IRQ_N(x) (USER_ILEV = 1 -> VME_IRQ_N(1),
USER_ILEV = 7 -> VME_IRQ_N(7)). Interrupt level 7 has the highest priority and interrupt level 1 has the lowest.
Since there, the interrupt handler acknowledges the interrupt by asserting a low state on the signal VME_IACK_N.
This signal will be transmitted to all modules and as well in the first module of the daisy-chain. The modules which
didn’t generate an interrupt just assert the VME_IACKIN_N signal to the VME_IACKOUT_N. A module which
generated an interrupt will detect the acknowledge at the falling edge and compare the VME_ADDR(3:1) with the
interrupt level register (USER_ILEV) to determine if it has the priority (depending on the level) to execute the
interrupt or not. In case of not, it will assign the VME_IACKIN_N to VME_IACKOUT_N. In the other case (the
corresponding module has the priority), the high state is asserted to the VME_IACKOUT_N signal in order to break
the daisy-chain and avoid other modules taking the interrupt acknowledge. During the acknowledge, the module
transfers the interrupt vector register defined by the user (USER_IVEC) on the VME data bus (VME_DATA_OUT).
When the data are valid, the VME controller drives the VME_DTACK_N signal low, allowing the master and
interrupt handler executing next commands.
On the user part, the interrupt is acknowledged with the signal USER_IACK which clears the pending interrupt
request.
Device Requirements
Family
Device
Utilization
Performance
COMB
SEQ
Total
SX-A
SX32A-STD
66 (4%)
135 (13%)
201 (7%)
138 MHz
ProASIC
PLUS
APA150-STD
n/a
n/a
295 (5%)
112 MHz
Axcelerator
AX500-STD
65 (2%)
135 (5%)
200 (3%)
159 MHz
Table 1: Device Utilization and Performance
Verification and Compliance
Complete functional and timing simulation has been performed on the VME using ModelSim 5.5e. This core has
also been used successfully in customer designs.


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