Datenblatt-Suchmaschine für elektronische Bauteile |
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MC-ACT-UL2LINK-VHDL Datenblatt(PDF) 3 Page - Actel Corporation |
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MC-ACT-UL2LINK-VHDL Datenblatt(HTML) 3 Page - Actel Corporation |
3 / 7 page RX MASTER The RX master is responsible for polling the PHYs and internal queues in order to send cells to the slave device. Signal Width Direction Description ING_CLK 1 Input 25/50 MHz Utopia Clock for all registers in this block ING_DATA 8/16 Input Utopia Data Bus. 8 or 16 bits selectable ING_ADDR 5 Output Utopia Address Bus used for polling ING_SOC 1 Input Utopia Start of Cell signal used to flag the first byte/word in the cell ING_ENB_N 1 Output Utopia Enable signal used for selection ING_CLAV 1 Input Utopia Cell Available signal used to indicate that the phy has a cell is ready for trans- mission ING_PRTY 1 Input Utopia Parity used for odd parity on EGR_DATA ING_PERR N Output Internal signal used to indicate that a parity error was detected on ING_DATA WR_DATA N*8/16 Output Internal FIFO Bus WR_ENB N Output Internal FIFO Write Enable Signal INCREMENT N Output Internal signal used to increment cell available counter A_FULL N Input Internal FIFO almost full flag indicates that the FIFO cannot accept another cell Table 3: RX Master Signal List RX FIFO The RX FIFO contains the RAM FIFO and the packet counter block. The packet counter is responsible for generating the cell available flags for the rest of the design. Every time a cell is written into the FIFO increment gets set and the cell count goes up, and when a cell is read decrement is set and the cell count goes down. The cell available “flag” is set when there is at least one cell in the FIFO that needs to be read. The FIFO operates in synchronous and asynchronous systems and can hold 9 cells. There is one FIFO per PHY polled. If there is a SOC-SOC error the FIFO will discard all previous data and use the current data as the first byte in the new cell. Signal Width Direction Description WR_CLK 1 Input Write Clock for the FIFO = ING_CLK for all write registers in this block WR_DATA N*8/16 Input Write data bus for FIFO WR_ENB N Input Write enable signal for FIFO INCREMENT N Input Increment signal for packet counter block A_FULL N Output Almost full for FIFO indicates that the FIFO does not have enough room for an ad- ditional cell. RD_CLK 1 Input System Clock for all read registers in this block RD_DATA N*8/16 Output Read data bus for the FIFO RD_ENB N Input Read enable signal for the FIFO DECREMENT N Input Decrement signal for packet counter block EMPTY N Output Indicates when FIFO is Empty Table 4: RX FIFO Signal List DATA FORMATTING The data will be written into the FIFO in 8/16 bit increments. If the 16-bit Utopia interface is selected then the MSB will be in bits (15:8) and the LSB will be in (7:0). MSB (15:8) LSB (7:0) Figure 1: Data Formatting |
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