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SN74ABT8543DL Datenblatt(PDF) 8 Page - Texas Instruments |
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SN74ABT8543DL Datenblatt(HTML) 8 Page - Texas Instruments |
8 / 25 page SN54ABT8543, SN74ABT8543 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS SCBS120E – AUGUST 1991 – REVISED JULY 1996 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 register overview With the exception of the bypass register, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register. instruction register description The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the three data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR. Table 3 lists the instructions supported by the ’ABT8543. The even-parity feature specified for SCOPE ™ devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPE ™ devices but are not supported by this device default to BYPASS. During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated, and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TDO TDI Bit 7 Parity (MSB) Bit 0 (LSB) Figure 2. Instruction Register Order of Scan data register description boundary-scan register The boundary-scan register (BSR) is 40 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin, two BSCs for each normal-function I/O pin (one for input data and one for output data), and one BSC for each of the internally decoded output-enable signals (OEA and OEB). The BSR is used to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output pins, and/or to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in Test-Logic-Reset, the value of each BSC is reset to logic 0. When external data is to be captured, the BSCs for signals OEA and OEB capture logic values determined by the following positive-logic equations: OEA + OEBA ) CEBA, and OEB + OEAB ) CEAB. When data is to be applied externally, these BSCs control the drive state (active or high-impedance) of their respective outputs. The BSR order of scan is from TDI through bits 39–0 to TDO. Table 1 shows the BSR bits and their associated device pin signals. |
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