SN54LV595A, SN74LV595A

8BIT SHIFT REGISTERS

WITH 3STATE OUTPUT REGISTERS

SCLS414N − APRIL 1998 − REVISED APRIL 2005

2

POST OFFICE BOX 655303

description/ordering information (continued)

These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.

The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage

register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output

state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both

clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLE

INPUTS

FUNCTION

SER

SRCLK

SRCLR

RCLK

OE

FUNCTION

X

X

X

X

H

Outputs QA−QH are disabled.

X

X

X

X

L

Outputs QA−QH are enabled.

X

X

L

X

X

Shift register is cleared.

L

↑

H

X

X

First stage of the shift register goes low.

Other stages store the data of previous stage, respectively.

H

↑

H

X

X

First stage of the shift register goes high.

Other stages store the data of previous stage, respectively.

X

X

X

↑

X

Shift-register data is stored in the storage register.