SN74ABT3613

64

× 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

9

POST OFFICE BOX 655303

almost-empty flag (AE)

The FIFO AE flag is synchronized to the port clock that reads data from its array (CLKB). The almost-empty state

is defined by the value of the AF and AE offset register (X). This register is loaded with one of four preset values

during a device reset (see

reset). An AE flag is low when the FIFO contains X or fewer long words in memory

and is high when the FIFO contains (X + 1) or more long words.

Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level of

fill; therefore, the AE flag of a FIFO containing (X + 1) or more long words remains low if two CLKB cycles have

not elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the second

low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition

to (X + 1) long words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle

(see Figure 11).

almost-full flag (AF)

The FIFO AF flag is synchronized to the port clock that writes data to its array (CLKA). The almost-full state is

defined by the value of the AF and AE offset register (X). This register is loaded with one of four preset values

during a device reset (see

reset). An AF flag is low when the FIFO contains (64 – X) or more long words in

memory and is high when the FIFO contains [64 – (X + 1)] or less long words.

Two low-to-high transitions of CLKA are required after a FIFO read for the AF flag to reflect the new level of fill;

therefore, the AF flag of a FIFO containing [64 – (X + 1)] or fewer words remains low if two CLKA cycles have

not elapsed since the read that reduced the number of long words in memory to [64 – (X + 1)]. An AF flag is

set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of long words

in memory to [64 – (X + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs

Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 12).

mailbox registers

Two 36-bit bypass registers (mail1, mail2) are on board the SN74ABT3613 to pass command and control

information between port A and port B without putting it in queue. A low-to-high transition on CLKA writes

A0–A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high.

A low-to-high transition on CLKB writes B0–B35 data to the mail2 register when a port-B write is selected by

(CSB, W/RB, and ENB) and both SIZ0 and SIZ1 are high. Writing data to a mail register sets the corresponding

flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low.

When the port-B data outputs (B0–B35) are active, the data on the bus comes from the FIFO output register

when either one or both SIZ1 and SIZ0 are low and from the mail1 register when both SIZ1 and SIZ0 are high.

The mail1 register flag (MBF1) is set high by a rising CLKB edge when a port-B read is selected by CSB, W/RB,

and ENB, and both SIZ1 and SIZ0 are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge

when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains

intact after it is read and changes only when new data is written to the register.