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SN74ACT3631PCB Datenblatt(PDF) 6 Page - Texas Instruments |
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SN74ACT3631PCB Datenblatt(HTML) 6 Page - Texas Instruments |
6 / 26 page SN74ACT3631 512 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS246G – AUGUST 1993 – REVISED APRIL 1998 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION W/RA I Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is low. detailed description reset The SN74ACT3631 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR) flag high, the almost-empty (AE) flag low, and the almost-full (AF) flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory. almost-empty flag and almost-full flag offset programming Two registers in the SN74ACT3631 are used to hold the offset values for the almost-empty and almost-full flags. The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF) flag offset register is labeled Y. The offset registers can be loaded with a value in three ways: one of two preset values is loaded into the offset registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-high transition on the RST input (see Table 1). Table 1. Flag Programming FS1 FS0 RST X AND Y REGISTERS† H H ↑ Serial load H L ↑ 64 L H ↑ 8 L L ↑ Parallel load from port A † X register holds the offset for AE; Y register holds the offset for AF. preset values If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of a RST low-to-high transition according to Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA. parallel load from port A To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA. The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset register of the SN74ACT3631 uses port-A inputs (A8 – A0). The highest number input is used as the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to 508. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM. |
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