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SN74ACT8994FN Datenblatt(PDF) 4 Page - Texas Instruments |
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SN74ACT8994FN Datenblatt(HTML) 4 Page - Texas Instruments |
4 / 11 page SN74ACT8994 DIGITAL BUS MONITOR IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER SCAS196E – JULY 1990 – REVISED DECEMBER 1996 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION CLK1, CLK2, CLK3 7, 8, 9 I Clock 1, 2, and 3. CLK1 – CLK3 provide various types of system clock and control signals to the DBM for the purpose of synchronizing test operations to the system under test. D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 6, 5, 4, 3, 2, 1, 27, 26, 25 24, 23, 22, 21, 20, 19, 18 I Data bus inputs. D15 – D0 form the 16-bit digital bus that is monitored by the DBM. Data that appears at this bus can be compressed into a 16-bit signature and/or stored in the 1024-word RAM. Each data bit can be individually masked during test operations. EQI 17 I Event-qualification input. EQI is used to receive an external (global) event signal from user-defined event-qualification logic. EQI can be configured to initiate test operations in the on-line mode. EQO 15 O Event-qualification output. EQO is used to transmit any of several internally generated status signals. EQO can be configured to transmit internal (local) event signals to external (global) event-qualification logic. GND 14 Ground PIO 16 I/O Polynominal input/output. PIO is used to cascade more than one DBM to provide signature analysis on a bus larger than 16 bits. Its configuration as an input or output for a particular DBM device depends on the significance (most, middle, or least) of that DBM in the scan path. TCK 11 I Test clock. One of four pins required by IEEE Standard 1149.1-1990. Scan operations of the DBM are synchronous to TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK. TDI 12 I Test data input. One of four pins required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected. TDO 13 O Test data output. One of four pins required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. TMS 10 I Test mode select. One of four pins required by IEEE standard 1149.1-1990. TMS directs the DBM through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. VCC 28 Supply voltage detailed description The general architecture of the DBM is shown in the functional block diagram. The DBM contains eight data registers and an instruction register that are accessed serially through the TAP. The TAP controller is a finite-state machine that issues control and enable signals throughout the device, based on its current state. The instruction register (IR) provides additional control signals that are specific to the current instruction. Test data is transmitted serially from TDI through the scan path to TDO. The IR or one of the eight data registers is always selected in the scan path by the TAP control signals issued to the TDO multiplexer. The 1024-word RAM can be used to store data from the bus being monitored during test operations. The RAM is accessed via the TAP interface when the RAM register (RAMR) is selected in the scan path. The event-qualification module (EQM) contains two data registers that contain configuration, compare, and mask data associated with on-line test operations. The EQM also contains the state machines for the eight protocols that include various start /stop, start /pause/resume, and do-while algorithms. These protocols operate synchronously to the clock signal generated by the programmable clock interface (PCI). The PCI generates a clock signal from one of 32 different logical combinations of CLK1, CLK2, CLK3, and TCK. The user configures the PCI through the control register (CTLR). |
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