Datenblatt-Suchmaschine für elektronische Bauteile |
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74LVC161284DLRG4 Datenblatt(PDF) 7 Page - Texas Instruments |
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74LVC161284DLRG4 Datenblatt(HTML) 7 Page - Texas Instruments |
7 / 12 page SN74LVC161284 19BIT BUS INTERFACE SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION Output (see Note C) tPHL tPLH From B or Y Output Under Test SLEW RATE A-TO-B OR A-TO-Y LOAD (Totem Pole) VOLTAGE WAVEFORMS MEASURED AT TP1 PROPAGATION DELAY TIMES (A to B) 2.7 V VOH VOL 0 V 62 Ω CL = 50 pF (see Note A) TP1 VCC CL = 50 pF (see Note A) Sink Load Source Load 1.4 V VOH − 1.4 V 62 Ω tPHL tPLH Input (see Note B) Output (see Note B) 1.4 V VOL + 1.4 V tw A-TO-B LOAD OR A-TO-Y LOAD (Open Drain) VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE 2.7 V VOH VOL 0 V 1.4 V 1.4 V 2 V 2 V 0.8 V 0.8 V tr tf TP1 From B or Y Output CL = 50 pF (see Note A) 500 Ω VCC NOTES: A. CL includes probe and jig capacitance. B. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10 µs for both low-to-high and high-to-low transitions. Slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and 1.9 V for the falling edge. C. Input rise and fall times are 3 ns. Rise and fall times (open drain) < 120 ns. D. The outputs are measured one at a time, with one transition per measurement. Input (see Note C) Figure 1. Load Circuits and Voltage Waveforms |
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Ähnliche Beschreibung - 74LVC161284DLRG4 |
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