Datenblatt-Suchmaschine für elektronische Bauteile |
|
TL16C754PN Datenblatt(PDF) 5 Page - Texas Instruments |
|
TL16C754PN Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 39 page TL16C754 QUAD UART WITH 64-BYTE FIFO SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Control Signals Modem Control Signals Divisor Bus Interface Control and Status Block Status Signals Control Signals Status Signals Baud-Rate Generator UART_CLK Receiver Block Logic Receiver FIFO 64-Byte Vote Logic Transmitter Block Logic Transmitter FIFO 64-Byte RX RX TX TX NOTE: The Vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a majority vote to determine the logic level received. The Vote logic operates on all bits received. functional description The TL16C754 UART is pin compatible with the TL16C554 and ST16C654 UARTs. It provides more enhanced features. All additional features are provided through a special enhanced feature register. The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the TL16C754 UART can be read at any time during functional operation by the processor. The TL16C754 UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers. The TL16C754 UART has selectable hardware flow control and software flow control. Both schemes significantly reduce software overhead and increase system efficiency by automatically controlling serial data flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses programmable Xon/Xoff characters. The UART will include a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216–1). The CLKSEL pin can be used to divide the input clock by 4 or by 1 to generate the reference clock during the reset. The divide-by-4 clock is selected when CLKSEL pin is a logic 0 or the divide-by-1 is selected when CLKSEL is a logic 1. |
Ähnliche Teilenummer - TL16C754PN |
|
Ähnliche Beschreibung - TL16C754PN |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |