Datenblatt-Suchmaschine für elektronische Bauteile |
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TP3057ADW Datenblatt(PDF) 3 Page - Texas Instruments |
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TP3057ADW Datenblatt(HTML) 3 Page - Texas Instruments |
3 / 17 page TP3054A, TP3057A, TP13054A, TP13057A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL DESCRIPTION NAME NO. DESCRIPTION ANLG GND 2 Analog ground. All signals are referenced to ANLG GND. BCLKR/CLKSEL 7 The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately, BCLKR/CLKSEL can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for the master clock in the synchronous mode. BCLKX is used for both transmit and receive directions (see Table 1). BCLKX 10 The bit clock that shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. DR 6 Receive data input. PCM data is shifted into DR following the FSR leading edge. DX 11 The 3-state PCM data output that is enabled by FSX. FSR 5 Receive-frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures 1 and 2 for timing details). FSX 12 Transmit-frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see Figures 1 and 2 for timing details). GSX 14 Analog output of the transmit input amplifier. GSX is used to externally set gain. MCLKR/PDN 8 Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. MCLKX 9 Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR TSX 13 Open-drain output that pulses low during the encoder time slot VBB 1 Negative power supply. VBB = – 5 V ± 5% VCC 4 Positive power supply. VCC = 5 V ± 5% VFRO 3 Analog output of the receive filter VFXI + 16 Noninverting input of the transmit input amplifier VFXI – 15 Inverting input of the transmit input amplifier |
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