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SN74SSQEA32882ZALR Datenblatt(PDF) 1 Page - Texas Instruments |
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SN74SSQEA32882ZALR Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 6 page 1 FEATURES APPLICATIONS DESCRIPTION/ORDERING INFORMATION SN74SSQEA32882 www.ti.com...................................................................................................................................................................................................... SCAS879 – JUNE 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select • JEDEC SSTE32882 Compliant Enable (QCSEN) input. • 1-to-2 Register Outputs and 1-to-4 Clock Pair First, when the QCSEN input pin is open or pulled Outputs Support Stacked DDR3 DIMMs high, the component has two chip select inputs, • CKE Powerdown mode for optimized system DCS0 and DCS1, and two copies of each chip select power consumption output, QACS0, QACS1, QBCS0 and QBCS1. This • 1.5V/1.35V Phase Lock Loop Clock Driver mode is the QuadCS disabled mode. Alternatively, when the QCSEN input pin is pulled low, the Buffers One Differential Clock Pair (CK and component has four chip select inputs DCS[3:0], and CK) and Distributes to Four Differential four chip select outputs, QCS[3:0]. This mode is the Outputs QuadCS enabled mode. • 1.5V/1.35V CMOS Inputs When QCSEN is high or floating, the device also • Checks Parity on Command and Address supports an operating mode that allows a single (CS-gated) Data Inputs device to be mounted on the back side of a DIMM • Supports Four Chip Selects array. This device can then be configured to keep the input bus termination (IBT) feature enabled for all • Configurable Driver Strength input signals independent of MIRROR. The SN74SSQEA32882. operates from a differential clock (CK and CK). Data are registered at the crossing of • DDR3 Registered DIMMs up to DDR3-1600 CK going high and CK going low. This data can either • DDR3L Registered DIMMs up to DDR3L-1333 be re-driven to the outputs or used to access internal • Single-, Dual- and Quad-Rank RDIMM control registers. Details are covered in the Function Tables (each flip-flop) with QCSEN = low. Input bus data integrity is protected by a parity function. All address and command input signals are This JEDEC SSTE32882-compliant, 28-bit 1:2 or summed; the last bit of the sum is then compared to 26-bit 1:2 and 4-bit 1:1 registering clock driver with the parity signal delivered by the system at the parity is designed for operation on DDR3 registered PAR_IN input one clock cycle later. If these two DIMMs with with VDD of 1.5 V and on DDR3L values do not match, the device pulls the open drain registered DIMMs with VDD of 1.35 V. output ERROUT low. The control signals (DCKE0, The SN74SSQEA32882 implements different DCKE1, DODT0, DODT1, and DCS[n:0]) are not part power-saving mechanisms to reduce thermal power of this computation. dissipation and to support system power-down states. The package design is optimal for high-density Power consumption is further reduced by disabling DIMMs. By aligning input and output positions unused outputs. towards DIMM finger-signal ordering and SDRAM All inputs are 1.5V and 1.35V CMOS-compatible. All ballout, the device de-scrambles the DIMM traces outputs are optimized to drive DRAM signals on and allows low crosstalk designs with low terminated traces in DDR3 RDIMM applications. interconnect latency. Edge-controlled outputs reduce Clock outputs Yn and Yn and control net outputs ringing and improve signal eye opening at the DxCKEn, DxCSn, and DxODTn can each be driven SDRAM inputs. with a different strength and skew to optimize signal integrity, compensate for different loading, and balance signal travel speed. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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