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CS2000-OTP Datenblatt(PDF) 2 Page - Cirrus Logic |
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CS2000-OTP Datenblatt(HTML) 2 Page - Cirrus Logic |
2 / 30 page CS2000-OTP DS758F1 2 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 PLL PERFORMANCE PLOTS ............................................................................................................... 8 4. ARCHITECTURE OVERVIEW ............................................................................................................... 9 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 9 4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 9 4.2.1 Fractional-N Source Selection for the Frequency Synthesizer .............................................. 10 5. APPLICATIONS ................................................................................................................................... 11 5.1 One Time Programmability ............................................................................................................ 11 5.2 Timing Reference Clock Input ........................................................................................................ 11 5.2.1 Internal Timing Reference Clock Divider ............................................................................... 11 5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 12 5.2.3 External Reference Clock (REF_CLK) .................................................................................. 12 5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 12 5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 13 5.4 Output to Input Frequency Ratio Configuration ............................................................................. 14 5.4.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 14 5.4.2 User Defined Ratio (RUD), Hybrid PLL Mode ....................................................................... 14 5.4.3 Ratio Modifier (R-Mod) .......................................................................................................... 15 5.4.4 Effective Ratio (REFF) .......................................................................................................... 15 5.4.5 Fractional-N Source Selection ............................................................................................... 15 5.4.5.1 Manual Fractional-N Source Selection for the Frequency Synthesizer ..................... 16 5.4.5.2 Automatic Fractional-N Source Selection for the Frequency Synthesizer ................. 16 5.4.6 Ratio Configuration Summary ............................................................................................... 17 5.5 PLL Clock Output ........................................................................................................................... 18 5.6 Auxiliary Output .............................................................................................................................. 18 5.7 Mode Pin Functionality ................................................................................................................... 19 5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 19 5.7.2 M2 Mode Pin Functionality .................................................................................................... 19 5.7.2.1 M2 Configured as Output Disable .............................................................................. 19 5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 19 5.7.2.3 M2 Configured as Auto Fractional-N Source Selection Disable ................................ 20 5.7.2.4 M2 Configured as Fractional-N Source Select .......................................................... 20 5.7.2.5 M2 Configured as AuxOutSrc Override ..................................................................... 20 5.8 Clock Output Stability Considerations ............................................................................................ 20 5.8.1 Output Switching ................................................................................................................... 20 5.8.2 PLL Unlock Conditions .......................................................................................................... 21 5.9 Required Power Up Sequencing for Programmed Devices ........................................................... 21 6. PARAMETER DESCRIPTIONS ........................................................................................................... 22 6.1 Modal Configuration Sets ............................................................................................................... 22 6.1.1 R-Mod Selection (RModSel[1:0]) ...........................................................................................22 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 23 6.1.3 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 23 6.1.4 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. 23 6.2 Ratio 0 - 3 ...................................................................................................................................... 23 6.3 Global Configuration Parameters ................................................................................................... 24 6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 24 |
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