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ATmega128-16AU Datenblatt(PDF) 97 Page - ATMEL Corporation |
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ATmega128-16AU Datenblatt(HTML) 97 Page - ATMEL Corporation |
97 / 386 page 97 2467S–AVR–07/09 ATmega128 (FOC0) strobe bit in normal mode. The OC0 Register keeps its value even when changing between waveform generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM01:0) bits have two functions. The waveform generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next compare match. Also, the COM01:0 bits control the OC0 pin output source. Figure 37 shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O registers, I/O bits, and I/O pins in the fig- ure are shown in bold. Only the parts of the General I/O Port Control Registers (DDR and PORT) that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the reference is for the internal OC0 Register, not the OC0 pin. Figure 37. Compare Match Output Unit, Schematic The general I/O port function is overridden by the output compare (OC0) from the waveform generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis- ter bit for the OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the pin. The port override function is independent of the waveform generation mode. The design of the output compare pin logic allows initialization of the OC0 state before the out- put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 104. Compare Output Mode and Waveform Generation The waveform generator uses the COM01:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no action on the OC0 Register is to be performed on the next compare match. For compare output actions in the non- PWM modes refer to Table 53 on page 105. For fast PWM mode, refer to Table 54 on page 105, and for phase correct PWM refer to Table 55 on page 106. A change of the COM01:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits. PORT DDR DQ DQ OCn Pin OCn DQ Waveform Generator COMn1 COMn0 0 1 FOCn clk I/O |
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