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BU1573KV Datenblatt(PDF) 9 Page - Rohm

Teilenummer BU1573KV
Bauteilbeschribung  Real Time Video Processor ICs
Download  13 Pages
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Hersteller  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BU1573KV Datenblatt(HTML) 9 Page - Rohm

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BU1572GUW, BU1573KV, BU1574KU
Technical Note
9/12
www.rohm.com
2009.04- Rev.B
© 2009 ROHM Co., Ltd. All rights reserved.
2.
RGB interface
2.1.
RGB interface timing
The input timing of image signal on RGB I/F is shown in Table 2.1-1.
The output timing of image signal on RGB I/F is shown in Table 2.1-2.
Symbol
Explanation
MIN.
TYP.
MAX.
UNIT
tDCLK
Clock Cycle
27.7
-
-
ns
dDCLK
Clock Duty
40
50
60
%
tODD
Decision of LCDDO from DCKO
-
-
5
ns
tOCD
Decision of LCDVSO or LCDHSO from DCKO
-
-
5
ns
3.
YUV interface
3.1.
YUV interface timing
The input timing of image signal on YUV I/F is shown in Table 3.1-1.
The output timing of image signal on YUV I/F is shown in Table 3.1-2.
Symbol
Explanation
MIN.
TYP.
MAX
UN
tDS
Camera setup period
(between the DCKI rising and falling edges)
8
-
-
ns
tDH
Camera holding period
(between the DCKI rising and falling edges)
8
-
ns
Symbol
Explanation
MIN.
TYP
MAX
UNI
tDS
Camera setup period
(between the CAMCKI rising and falling edges)
8
-
-
ns
tDH
Camera holding period
(between the CAMCKI rising and falling edges)
8
-
ns
Symbol
Explanation
MIN.
TYP.
MAX.
UNIT
tPCLK
Clock Cycle
27.7
-
-
ns
dPCLK
Clock Duty
40
50
60
%
tODD
Decision of CAMDO from CAMCKO
-
-
5
ns
tOCD
Decision of CAMVSO or CAMHSO from CAMCKO
-
-
5
ns
Table 2.1-1
BU1572GUW/BU1573KV
RGB interface input timing
Table 2.1-2
BU1572GUW/BU1573KV Image signal output timing
LCDVSI
LCDHSI
LCDDI0
-LCDDI17
DCKI
(CKPOL=“0”)
DCKI
(CKPOL=“1”)
tDS
tDH
LCDVSO
LCDDO
[17:0]
LCDHSO
DCKO
tDCLK
tOCD
tOCD
tODD
Table 3.1-1
BU1574KU
YUV interface input timing
CAMVSI
CAMHSI
CAMDI0
-CAMDI7
CAMCKI
(CKPOL=“1”)
CAMCKI
(CKPOL=“0”)
tDS
tDH
Table 3.1-2
BU1574KU Image signal output timing
CAMVSO
CAMDO[7:0]
CAMHSO
CAMCKO
tPCLK
tOCD
tOCD
tODD


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