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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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X1205V8I Datenblatt(PDF) 6 Page - Xicor Inc. |
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X1205V8I Datenblatt(HTML) 6 Page - Xicor Inc. |
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6 / 22 page  X1205 – Preliminary Information REV 1.0.9 8/29/02 Characteristics subject to change without notice. 6 of 22 www.xicor.com INTERRUPT CONTROL REGISTER (INT) Interrupt Control and Status Bits (IM, AL1E, AL0E) There are two Interrupt Control bits, Alarm 1 Interrupt Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically enable or disable the alarm interrupt signal output (IRQ). The interrupts are enabled when either the AL1E and AL0E bits are set to “1”, respectively. Two volatile bits (AL1 and AL0), associated with the two alarms respectively, indicate if an alarm has happened. These bits are set on an alarm condition regardless of whether the IRQ interrupt is enabled. The AL1 and AL0 bits in the status register are reset by the falling edge of the eighth clock of a read of the register containing the bits. Pulse Interrupt Mode The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence an repetitive or recurring alarm can be set for every nth second, or nth minute, or nth hour, or nth date, or for the same day of the week. The pulsed interrupt mode can be consid- ered a repetitive interrupt mode, with the repetition rate set by the time setting fo the alarm. The Pulse Interrupt Mode is enabled when the IM bit is set. The Alarm IRQ output will output a single pulse of short duration (approximately 10-40ms) once the alarm condition is met. If the interrupt mode bit (IM bit) is set, then this pulse will be periodic. ON-CHIP OSCILLATOR COMPENSATION Digital Trimming Register (DTR) — DTR2, DTR1 and DTR0 (Non-Volatile) The digital trimming Bits DTR2, DTR1 and DTR0 adjust the number of counts per second and average the ppm error to achieve better accuracy. DTR2 is a sign bit. DTR2=0 means frequency compensation is > 0. DTR2=1 means frequency compensation is < 0. DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm adjustment and DTR0 gives 20 ppm adjustment. A range from -30ppm to +30ppm can be represented by using three bits above. Table 3. Digital Trimming Registers Analog Trimming Register (ATR) (Non-volatile) Six analog trimming Bits from ATR5 to ATR0 are pro- vided to adjust the on-chip loading capacitance range. The on-chip load capacitance ranges from 3.25pF to 18.75pF. Each bit has a different weight for capaci- tance adjustment. In addition, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm range from +116ppm to -37ppm to the nominal frequency compensation. The combination of digital and analog trimming can give up to +146ppm adjustment. The on-chip capacitance can be calculated as follows: CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF Note that the ATR values are in two’s complement, with ATR(000000) = 11.0pF, so the entire range runs from 3.25pF to 18.75pF in 0.25pF steps. The values calculated above are typical, and total load capacitance seen by the crystal will include approxi- mately 2pF of package and board capacitance in addi- tion to the ATR value. See Application section and Xicor’s Application Note AN154 for more information. IM Bit Interrupt / Alarm Frequency 0 Single Time Event Set By Alarm 1 Repetitive / Recurring Time Event Set By Alarm DTR Register Estimated frequency PPM DTR2 DTR1 DTR0 0 0 0 0 (default) 0 1 0 +10 0 0 1 +20 0 1 1 +30 10 0 0 1 1 0 -10 1 0 1 -20 1 1 1 -30 |
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