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74AHCT2G241GD Datenblatt(PDF) 8 Page - NXP Semiconductors |
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74AHCT2G241GD Datenblatt(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74AHC_AHCT2G241_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 January 2009 8 of 16 NXP Semiconductors 74AHC2G241; 74AHCT2G241 Dual buffer/line driver; 3-state 12. Waveforms Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. The input (nA) to output (nY) propagation delays mna230 tPHL tPLH VM VM nA input nY output GND VI VOH VOL Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The input (1OE) to output 1Y enable and disable times 001aaa411 tPLZ tPHZ outputs disabled outputs enabled outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH 1OE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM VOH − 0.3 V VOL + 0.3 V |
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