AD80066

Rev. A | Page 7 of 20

ANALOG

INPUTS

CDSCLK1

PIXEL n

PIXEL (n + 1)

PIXEL (n + 2)

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

NOTES

1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS LOW.

LOW

BYTE

HIGH

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

PIXEL (n – 4)

PIXEL (n – 4)

PIXEL (n – 3)

PIXEL (n – 3)

PIXEL (n – 2)

PIXEL (n – 2)

Figure 6. 1-Channel CDS Mode Timing

PIXEL n (A, B, C, D)

D(n)

D(n)

A(n)

A(n)

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

PIXEL (n + 1)

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1)

Figure 7. 4-Channel SHA Mode Timing