74HC138

http://onsemi.com

5

Figure 1.

50%

GND

Figure 2.

VALID

VALID

OUTPUT Y

50%

GND

90%

50%

10%

OUTPUT Y

INPUT CS1

90%

50%

10%

INPUT A

SWITCHING WAVEFORMS

GND

OUTPUT Y

INPUT

CS2, CS3

90%

50%

10%

90%

50%

10%

Figure 3.

*Includes all probe and jig capacitance

Figure 4. Test Circuit

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

PIN DESCRIPTIONS

ADDRESS INPUTS

A0, A1, A2 (Pins 1, 2, 3)

Address inputs. These inputs, when the chip is selected,

determine which of the eight outputs is active−low.

CONTROL INPUTS

CS1, CS2, CS3 (Pins 6, 4, 5)

Chip select inputs. For CS1 at a high level and CS2, CS3

at a low level, the chip is selected and the outputs follow the

Address inputs. For any other combination of CS1, CS2, and

CS3, the outputs are at a logic high.

OUTPUTS

Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)

Active−low Decoded outputs. These outputs assume a

low level when addressed and the chip is selected. These

outputs remain high when not addressed or the chip is not

selected.