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MC14013 Datenblatt(PDF) 1 Page - Motorola, Inc |
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MC14013 Datenblatt(HTML) 1 Page - Motorola, Inc |
1 / 6 page MOTOROLA CMOS LOGIC DATA 45 MC14013B Dual Type D Flip-Flop The MC14013B dual type D flip–flop is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each flip–flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip–flops for counter and toggle applications. • Static Operation • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge–Clocked Flip–Flop Design Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive–going edge of the clock pulse • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Pin–for–Pin Replacement for CD4013B MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C TRUTH TABLE Inputs Outputs Clock† Data Reset Set Q Q 0 0 0 0 1 1 0 0 1 0 X 0 0 Q Q X X 1 0 0 1 X X 0 1 1 0 X X 1 1 1 1 X = Don’t Care † = Level Change No Change MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14011B/12B (see pg 6-5) MC14011UB/12UB (see pg 6-14) MC14013B L SUFFIX CERAMIC CASE 632 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 646 D SUFFIX SOIC CASE 751A BLOCK DIAGRAM 10 11 9 8 4 3 5 6 12 13 2 1 S S R R D C D C Q Q Q Q VDD = PIN 14 VSS = PIN 7 |
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