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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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KM4132G271A-8 Datenblatt(PDF) 3 Page - Samsung semiconductor |
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KM4132G271A-8 Datenblatt(HTML) 3 Page - Samsung semiconductor |
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3 / 48 page  KM4132G271A CMOS SGRAM Rev.0 (August 1997) PIN CONFIGURATION DESCRIPTION PIN NAME INPUT FUNCTION CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMi CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one clock +tSS prior to new command. Disable input buffers for power down in standby. A0 ~ A8 Address Row / Column addresses are multiplexed on the same pins. Row address : RA0 ~ RA8, Column address : CA0 ~ CA7 A9(BA) Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and Row precharge. DQMi Data Input/Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active.(Byte Masking) DQi Data Input/Output Data inputs/outputs are multiplexed on the same pins. DSF Define Special Function Enables write per bit, block write and special mode register set. VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground |
Ähnliche Teilenummer - KM4132G271A-8 |
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Ähnliche Beschreibung - KM4132G271A-8 |
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